1. Field of the Invention
The present invention relates to memory circuits and, in particular, to a circuit capable of extremely high speed detection of an external address transition and generation of an address transition detection pulse while minimizing capacitive loading on the address buffer elements.
2. Discussion of the Prior Art
High speed memory circuits require the generation of a pulse upon detection of an external address transition. The address transition detection (ADT) pulse is utilized for deselecting and selecting memory cells, equalizing critical nodes within the memory, initiating data sensing in the memory storage elements and ultimately providing extremely fast access to the addressed data. Thus, the access time of a memory chip is a direct function of the delay between the occurrence of an address transition and the generation of the address transition detection pulse.
FIG. 1 shows a conventional address buffer and address transition detection (ATD) circuit that utilizes a pair of delay chains to feed a NOR gate network. The NOR gate network provides an output which, after propagation through a final delay stage, serves as an address transition detection pulse ATD0 for a memory array.
As further shown in FIG. 1, the address transition detection pulse ATD0 is provided to an n-channel pull-down transistor the drain of which is connected to a common address transition detection node for all address buffers in the array. A p-channel pull-up device returns the common node to logic high at the end of the address transition detection pulse.